Onsite opportunities Layout & Design

Hurry !!!!! Up!!!!!!

Referral Drive @ Malaysia Location.




Permanent: IC Layout & Design Engineer 

• Layout of integrated circuits in Cadence Virtuoso analog Intel tools like GenA
• Work according to project planning, provide feedback concerning layout planning to the project leader and organize own work

Skills:

• Minimum Experience with fibfet tech 3+ years in analog ,digital ,memory layout and design
• Tools:Intel GenA or anything ,must have 22nm to 7nm experience .
• Digital Layout/backend background
• Experience in working with Synposis
• RTL Design knowledge

Send your update Resume: 

referraldrive@yahoo.com

ANALOG IC LAYOUT INTERVIEW QUESTIONS-2

1. How do you choose height of Standard cells?

 2.What are the constraints you will follow while doing

 standard cells.

3.How you will  take care power in standard cells?

1.what are the difference between higher and lower node 

technologies ?

2.what is poly pitch?

3.cmos and finfet difference ?? Advantages

 and disadvantages? and why?

1.Fabrication of FinFet?

2.what are the challenges did you faced lower node technologies?

3.what is mean by Fins?

 1.How do you plan for device placement?

2.How you will identify Analog and Digital layout?

3.which one you will give more priority 

Analog or digital layout?

* How do you separate in layout.

 1.how do you calculate metal width and length?

2.what are the ways to reduce metal resistance?

    

3.what is mean by metal stag?

4.How do you choose power metal ?

4.High speed layout how you will reduce resistance ?

5.what is mean by contact and via?

 How many vias you will use and how it will help to reduce 

resistance.

6.what is mean by resistance shielding?

ANALOG IC LAYOUT INTERVIEW QUESTIONS -BASICS

Hello,Guys!!!!!!!!!!!!!!!!!!!!!

I am just sharing my personal experiences while facing ANALOG IC LAYOUT Interview Questions!!!!!!!!!!!!

Let’s start from the basics and hopefully will answer all questions later.

1.Draw the symbol of NMOS & PMOS Transistor? Explain each terminal and where its connecting?

2.Explain the operation of NMOS Transistor?

3. Transistor Second-Order Effects

 *What is Threshold voltage?

  *What is hot electron effect?

  *what is channel length modulation?

4.what is subthreshold leakages?

5.What is mean by Latch-up? What are the solution to solve latch-up issues? How you will take care while doing layout?

6.What is mean by Guard ring? What are types of Guard rings? How it will help to reduce latch-up?

   What is Deep N-well guarding?

7.what is meant by antenna? what is the solution to reduce antenna effect in the layout?

* From where accumulated charges are coming?

 * Where is the discharge path?

*  How do jumper and diode will help?

* No place to add diode and jumper what you will do?

8.Explain about shielding? Types of shielding? What are the signals you will do shielding and why?

Where you will connect shielded lines and why? Without shielding what will happen?

9.what is mean by cross-talk?

10. Describe Electromigration effect? & ways to reduce Electromigration during layouts?

11.what is ESD? how you will fix ESD problems in the layout?

12.what is WPE, LOD & STI? Explain with diagram

13.What is matching? Types of matching and explain one by one? What will happen not doing matching?

* how you can match resistor & capacitor layouts?

 *what are advantages and disadvantages of Common centroid & interdigitated patterns?

 *how to improve the match of the current mirror, differential pairs?

 *What is dummy Transistors?

14. Describe DFM?

15.what is STD cells? How you will decide the height of STD cells?

 * what is mean by Track?

* What is mean by a pitch?

16.Draw the diagram of INV, NAND and OR gates.

(((((((continue next slide will update soon.! Thanks for watching!!!!!!!!!